1. Field of the Invention
The present invention relates to a method of manufacturing a flash electrically erasable programmable read-only memory (EEPROM), and particularly to a method of manufacturing a flash EEPROM which can reduce the topology produced by an oxide film formed in a buried bit line in which a source region and a drain region are contained.
2. Information Disclosure Statement
FIG. 1 is a layout showing general split gate type flash EEPROM cells and FIG. 2 is a sectional view of the cells taken along line X--X' of FIG. 1.
Referring to FIGS. 1 and 2, an active region A and a field region B are defined by an isolation technology. The active region A is defined to include bit line regions C1 and C2 and a channel region. A field oxide film (not shown) is formed on a silicon substrate 1 of the field region B by an oxidization process. Floating gates 3 are formed along both sides of the bit line region C2 and for each cell region. Control gates 5 are longitudinally formed along both sides of the bit line region C2. A tunnel oxide film 2 is formed between the floating gate 3 and the silicon substrate 1. An interlayer dielectric film 4 is formed between the floating gate 3 and the control gate 5. Impurity diffusion layers 6 are formed in the source bit line region C1 and the drain bit line region C2 by means of a source/drain impurity ion implantation process. A select gate oxide film 7 is formed at an exposed portion of the silicon substrate 1 by an oxidation process, during which a thick oxide film 8 is formed on the impurity diffusion layers 6 as a result of the high rate of oxidation on the layers 6. As the oxide film 8 formed on the impurity diffusion layer 6 becomes thicker, the topology becomes higher. Due to such high topology, a subsequent process such as the formation of the select gate (not shown) becomes more difficult, thereby causing a problem of the electrical characteristics of the cell being degraded.
Therefore, the object of the present invention is to provide a method of manufacturing flash EEPROM cells which can improve the electrical characteristics of the cell by decreasing the topology produced by the oxide film formed in a bit line in which a source region and a drain region are contained.